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Optimization of Non-Volatile FPGA

Date: 2017-02-28
Writer:

 非易失性FPGA的优化

I. Details of the lecture

Topic: Optimization of Non-Volatile FPGA 

Time: Wednesday, December 14, 2016, 12:10 - 13:10

Venue: Room 10-206, Rohm Building, Tsinghua University

Speaker: Hu Jingtong, Assistant Professor, Oklahoma State University

II. Introduction to the speaker  

1998-2007: Bachelor’s degree, School of Computer Science and Technology, Shandong University

2004-2009: PhD, Department of Computer Science, University of Texas at Dallas

He currently serves as an assistant professor at the School of Electrical and Computer Engineering at Oklahoma State University. He received a bachelor’s degree from the School of Computer Science and Technology, Shandong University in 2007. His research interests include embedded systems, FPGA, non-volatile memory and wireless sensor networks. His research was sponsored by the National Science Foundation (NSF), the Air Force Research Laboratory (AFRL) and Altera. He has served as a member in technical planning committees for many international conferences such as ASP-DAC, DATE, DAC, ESWEEK, RTSS, etc. He also has won the OSU CEAT Outstanding New Teacher Award, the Women’s Professor Committee Research Award and the Air Force Summer Teacher Fellowship.

III. Content of lecture

Because traditional SRAM-based FPGA faces such problems as scalability, latency, power consumption, and low bit error rate, researchers have proposed the use of non-volatile memory (NVM) in FPGA. Although NVM offers great potential to overcome these limitations, they pose a series of new design challenges to FPGA: the slow write performance of NVM may reduce reconfiguration speed. If frequent reconfigurations are performed, the write durability may limit the life of FPGA. In order to improve the performance and life of NVM-based FPGA, we propose several similarity drive reconstruction methods to speed up the reconstruction process and extend the life of NVM-based FPGA. The contents of the Look-Up-Table (LUT) and the topology of the netlist are taken into consideration. Experiment with standard circuit benchmarks shows that the proposed algorithm can significantly eliminate writes during reconfiguration, thereby effectively improving performance and robustness of FPGA.

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