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Flash performance and reliability optimization: from chip, controller to system

Date: 2017-02-28
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 闪存性能和可靠性优化:从芯片、控制器到系统

i. Seminar Information

Topic: Flash performance and reliability optimization: from chip, controller to system

Time: Wednesday, December 14, 2016, 12:10 - 13:10

Location: Room 10-206, Rohm Building, Tsinghua University

Speaker: Chun Jason Xue, Associate Professor, City University of Hong Kong

ii. An Introduction of the speaker

       1993-1997: Bachelor's degree, Computer Engineering, Architecture, University of Texas at Arlington

       2001-2003: Master's degree, Computer Science, University of Texas at Dallas

       2003-2007: PhD, Computer Science, University of Texas at Dallas

       He currently serves as an associate professor of computer science at the City University of Hong Kong. His research interests include non-volatile memory, and embedded and real-time systems. He is currently the deputy chief editor of ACM affairs of embedded computing systems, deputy chief editor of CPS ACM affairs, and the editor of ACM Transactions on Storage. He is the co-chair of TPC, co-chair of LCTES in 2015, and co-chair of TPC of ISVLSI2016. He serves as a TPC member at top conferences such as DAC, DATE, RTSS, RTAS, CODS, EMSOFT and ISLPED.

iii. Contents of the Seminar

This lecture consists of three parts. In the first part, he introduces the background and related work of Flash chip-level design. Since the quality and reliability of written data is highly correlated with the Flash programming speed, how to use these features is very important for flash-based storage systems. Moreover, the flash memory of existing technology has the problems of reduced reliability and significant process variations. To address these issues, some measures will be proposed to optimize the performance and reliability of flash memory. In the second part, he introduces the flash controller design, including parallelism exploration of performance and the reliability of error correction code. We are especially interested in low-density parity check codes, which have sound error correction capabilities but have high costs in terms of decoding performance. We will also discuss how to use important process variations to improve performance and life. In the third part, he will discuss the system-level work of flash-based storage devices. The current system of flash memory has not made full use of the characteristics of flash memory. In this section, he will introduce work on the fragmentation problem on smartphones and discuss cross-layer supported I/O scheduling algorithms to improve performance.

 

 


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