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Advanced ADC Design Techniques

Date: 2017-11-08
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Advanced ADC Design Techniques

I. Details of the lecture 

Topic: Advanced ADC Design Techniques

Time: 10:00AM, November 9th, 2017

Location: Room 10-206, Rohm Building, Tsinghua University

Speaker: Nan Sun   Associate Professor, Dept. of Electrical and Computer Engineering, University of Texas at Austin

II. Introduction to the speaker 

Nan Sun is Associate Professor in the Department of Electrical and Computer Engineering at the University of Texas at Austin. He received the B.S. degree from Tsinghua University, Beijing, China in 2006, where he ranked top in Department of Electronic Engineering and graduated with the highest honor and the Outstanding Undergraduate Thesis Award. He received the Ph.D. degree from Harvard University in 2010. Dr. Sun holds the AMD Development Chair at UT Austin. He received the NSF Career Award in 2013 and Jack Kilby Research Award from UT Austin in 2015. He also received Samsung Fellowship, Hewlett Packard Fellowship, and Analog Devices Outstanding Student Designer Award in 2003, 2006, and 2007, respectively. He won Harvard Teaching Award in three consecutive years: 2008, 2009, and 2010. He serves in the TPC of IEEE Custom Integrated Circuits Conference and Asian Solid-State Circuit Conference. He is Associate Editor for IEEE Transactions on Circuits and Systems – I: Regular Papers.

III. Content of lecture 

This talk presents our recent studies on advance ADC design techniques, including hybrid noise-shaping SAR ADC, high-speed SAR ADC with sparkle code correction, and time-interleaved ADC with fast background timing skew calibration. First, I will present a  DS SAR ADC. It does not require any op-amp based active integrator that is scaling unfriendly and power consuming. Instead, it uses simple passive switched capacitor circuits to perform integration, dynamic gain and summation, leading to high power efficiency, high scaling compatibility, and low design complexity. Second, I will talk about how to correct sparkle code due to comparator metastability in a high-speed SAR ADC. The proposed method is based on comparator decision time detection, and it can reduce the sparkle code rate by several orders of magnitude. Moreover, it can enhance the ADC resolution by 1-bit based on time-domain quantization. It also ensures robustness against PVT by devising a novel background calibration technique. Last but not least, I will present a novel variance-based timing-skew calibration technique for time-interleaved SAR ADC. The proposed technique is able to accelerate the background convergence loop by over a thousand times, while achieving low hardware complexity and low power. 

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